- likely reuse the sub-system architecture (module);

- leverage chips in the markets, and create own differentiated chiplets/interface;

- strategy for design-for-supply chains;

- decent PDC (product development cycle) and time-to-markets revision.

per NDA (non-disclosure agreement), we start with (as-is) BOM1 

and discuss (to-be) BOM2 migration plans.

=> high-level spec of revised BOM/architect

1. high-level divide-and-conquer planning;

2. draft system PPA$ (performance, power, form-factor, total cost);

3. thermal-aware path-finding for chiplets/package stacking ;

=> adjust the BOM/architect concepts

4. matching IP vs. technology (process, sip, designs);

5. re-usability among applications: industry, automotive, space, etc.

6. practical design for supplychain options & operations.

=> talk to the experienced expertise.

DfM (design for manufacturing) &

MfD (manufacturing for design)

are complicated/comprehensive methodologies

from OEM to ODM/OBM paths.

Under NDA and given BOM lists, the options are

- D2W: die-to-wafer stacking;

- W2W: wafer-to-wafer hybrid bonding;

the pilot-line gives a PoC-trial, before the decent design/process co-optimization... 

(it-was) >5 years for MEMS 0->1 PDC efforts;

(to-be) <1.5 years with proven-MEMS IP+process (minor tuning),

we help to improve 1->2/N PDC in <2 years, by decent/flexible 

"AinterposerX" methodologies.

(it-was) MEM-KGD for dram/flash/sram in PCB/PoP assembly;

(to-be) MEM-hybrid for D2W, W2W interposer integration.